公开(公告)号：US20200081835A1

公开(公告)日：2020-03-12

申请号：US16126907

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： REN WANG ,  RAANAN SADE ,  YIPENG WANG ,  Tsung-Yuan TAI ,  SAMEH GOBRIEL

IPC: G06F12/0811 ,  G06F17/30 ,  G06F9/38

Abstract: An apparatus and method for prioritizing transactional memory regions. For example, one embodiment of a processor comprises: a plurality of cores to execute threads comprising sequences of instructions, at least some of the instructions specifying a transactional memory region; a cache of each core to store a plurality of cache lines; transactional memory circuitry of each core to manage execution of the transactional memory (TM) regions based on priorities associated with each of the TM regions; and wherein the transactional memory circuitry, upon detecting a conflict between a first TM region having a first priority value and a second TM region having a second priority value, is to determine which of the first TM region or the second TM region is permitted to continue executing and which is to be aborted based, at least in part, on the first and second priority values.

公开(公告)号：US20200097291A1

公开(公告)日：2020-03-26

申请号：US16140196

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： CHRISTOPHER J. HUGHES ,  BRET TOLL ,  ALEXANDER HEINECKE ,  DAN BAUM ,  ELMOUSTAPHA OULD-AHMED-VALL ,  RAANAN SADE ,  ROBERT VALENTINE ,  MARK CHARNEY

IPC: G06F9/30 ,  G06F9/48

Abstract: An apparatus and method for tile-based gather and scatter operations. For example, one embodiment of a processor comprises: a destination tile register to store a 2-D arrangement of data elements; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch a tile gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the tile gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register and to load the data elements from the system memory addresses to the destination tile register.

公开(公告)号：US20210200686A1

公开(公告)日：2021-07-01

申请号：US16728573

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： RON GABOR ,  RAANAN SADE ,  IGOR YANOVER ,  ASSAF ZALTSMAN ,  TOMER STARK

IPC: G06F12/1009 ,  G06F9/30

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US20210200684A1

公开(公告)日：2021-07-01

申请号：US16728527

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： RON GABOR ,  ENRICO PERLA ,  RAANAN SADE ,  IGOR YANOVER ,  TOMER STARK ,  JOSEPH NUZMAN

IPC: G06F12/0895 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/14 ,  G06F9/30 ,  G06F11/30

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.