公开(公告)号：US10700688B1

公开(公告)日：2020-06-30

申请号：US16221388

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Yongping Fan ,  Dan Zhang ,  Bo Xiang

IPC: G04F10/00 ,  H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03L7/093

Abstract: Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.