公开(公告)号：US20180294272A1

公开(公告)日：2018-10-11

申请号：US15798352

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Darwin Fan ,  Sateesh Koka ,  Gordon Haller ,  John Hopkins ,  Shyam Surthi ,  Anish Khandekar

IPC: H01L27/11524 ,  H01L21/28 ,  H01L27/11556

Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.