公开(公告)号：US10515973B2

公开(公告)日：2019-12-24

申请号：US15828039

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen W. Jungroth ,  David S. Meyaard ,  Khaled Hasnat

IPC: H01L27/11531 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

公开(公告)号：US20190043874A1

公开(公告)日：2019-02-07

申请号：US15828039

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen W. Jungroth ,  David S. Meyaard ,  Khaled Hasnat

IPC: H01L27/11531 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11573

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.