公开(公告)号：US20230076831A1

公开(公告)日：2023-03-09

申请号：US17469634

申请日：2021-09-08

Applicant: Intel Corporation

Inventor： Praveen Kumar Kalsani ,  Ahmed Reza ,  Liu Liu ,  Deepak Thimmegowda ,  Zengtao Tony Liu ,  Sriram Balasubrahmanyam

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

Abstract: An embodiment of a memory device may include a substrate, a first memory array of three-dimensional (3D) NAND cells disposed on the substrate, an isolation trench disposed on the substrate adjacent to the first memory array, and an input/output (IO) contact positioned within the isolation trench. Other embodiments are disclosed and claimed.

公开(公告)号：US10515973B2

公开(公告)日：2019-12-24

申请号：US15828039

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen W. Jungroth ,  David S. Meyaard ,  Khaled Hasnat

IPC: H01L27/11531 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

公开(公告)号：US20190043873A1

公开(公告)日：2019-02-07

申请号：US16122266

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Khaled Hasnat ,  Prashant Majhi ,  Deepak Thimmegowda

IPC: H01L27/11529 ,  H01L27/11573 ,  H01L29/786 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11531

Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.

公开(公告)号：US09865357B1

公开(公告)日：2018-01-09

申请号：US15395700

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Pranav Kalavade ,  Aaron Yip ,  Shantanu R. Rajwade

IPC: G11C16/26 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C5/063 ,  G11C5/145 ,  G11C8/00 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: Technology for performing read operations in a memory device or system is described. The device or system can include an array of memory cells. The device or system can include a first decode circuit, and can further include a second decode circuit. The device or system can include a voltage regulator configured to perform a read operation by providing, based on one or more signals received from at least one of the first decode circuit or the second decode circuit, a voltage to a selected plane or a selected sub-plane in the array of memory cells.

公开(公告)号：US11653496B2

公开(公告)日：2023-05-16

申请号：US17032239

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Chang Wan Ha ,  Chuan Lin ,  Deepak Thimmegowda ,  Zengtao Liu ,  Binh N. Ngo ,  Soo-yong Park

IPC: H01L27/11 ,  H01L27/1158 ,  H01L29/10 ,  G11C16/04

CPC classification number: H01L27/1158 ,  G11C16/0466 ,  G11C16/0483 ,  H01L29/1033

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

公开(公告)号：US20150371925A1

公开(公告)日：2015-12-24

申请号：US14310391

申请日：2014-06-20

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Roger Lindsay ,  Minsoo Lee

IPC: H01L23/48 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Technologies for routing access lines in non-volatile memory are described. In some embodiments the technologies include forming one or more through array vias in a portion of a memory array in a non-volatile memory, such as in an array region or peripheral region, one or more access lines may be routed through the through array via, instead of within a region above or below an array or peripheral region of the memory array. This can enable alternative routing configurations, and may enable additional access lines to be routed without increasing or substantially increasing the block height of the non-volatile memory. Non-volatile memory employing such technologies is also described.

Abstract translation: 描述了用于在非易失性存储器中路由接入线路的技术。 在一些实施例中，技术包括在诸如阵列区域或外围区域的非易失性存储器中的存储器阵列的一部分中形成一个或多个贯穿阵列通孔，一个或多个访问线路可以经过穿通阵列经由 而不是在存储器阵列的阵列或外围区域的上方或下方的区域内。 这可以实现替代的路由配置，并且可以使附加的接入线路可以不增加或显着增加非易失性存储器的块高度。 还描述了采用这种技术的非易失性存储器。

公开(公告)号：US20230200063A1

公开(公告)日：2023-06-22

申请号：US17559725

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Chang Wan Ha ,  Md Rezaul Karim Nishat ,  Liu Liu ,  Yuanrong Shui ,  Kwame Eason ,  Ahmed Reza ,  Hoon Koh

IPC: H01L27/11578 ,  H01L27/11551 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04 ,  G11C8/14

CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L23/481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/0483 ,  G11C8/14

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

公开(公告)号：US20220399057A1

公开(公告)日：2022-12-15

申请号：US17343584

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Chang Wan Ha ,  Deepak Thimmegowda ,  Hoon Koh ,  Richard M. Gularte ,  Liu Liu ,  David Meyaard ,  Ahsanur Rahman

IPC: G11C16/04

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

公开(公告)号：US10804280B2

公开(公告)日：2020-10-13

申请号：US16122266

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Khaled Hasnat ,  Prashant Majhi ,  Deepak Thimmegowda

IPC: H01L27/11529 ,  H01L27/11573 ,  H01L29/786 ,  H01L27/11531 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575

Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20200152650A1

公开(公告)日：2020-05-14

申请号：US16184641

申请日：2018-11-08

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen Jungroth ,  Khaled Hasnat ,  David Meyaard ,  Surendranath C. Eruvuru

IPC: H01L27/11556 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11519

Abstract: Embodiments of the present disclosure are directed towards a memory device with a split staircase, in accordance with some embodiments. In one embodiment, the memory device includes one or more pillars disposed in a die, and a plurality of wordlines formed in a stack of multiple tiers and coupled with the one or more pillars. At least some of the wordlines are split across the tiers into at least first and second portions. Respective ends of at least some wordlines of at least one of the first or second portions, at a location of the split, are exposed to provide electrical coupling with other components of the device. Other embodiments may be described and/or claimed.