公开(公告)号：US11575521B2

公开(公告)日：2023-02-07

申请号：US16455967

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  David Wheeler ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/32 ,  H04L9/06

Abstract: In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.

公开(公告)号：US11567733B2

公开(公告)日：2023-01-31

申请号：US16849103

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US20220100475A1

公开(公告)日：2022-03-31

申请号：US17541247

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US11057207B2

公开(公告)日：2021-07-06

申请号：US16235507

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： David Wheeler ,  Geoffrey Cooper

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/00 ,  H04L9/06

Abstract: The present disclosure is directed to systems and methods of providing a trusted ownership re-key with attestation in a device. The device includes processor circuitry that incorporates TEE circuitry. The TEE circuitry generates an AAIK and encrypts the AAIK using HMAC. The TEE circuitry forms a first message using the HMAC, a public DAK assigned to the device, and a device signature. The TEE circuitry sends an encrypted first message to the manufacturer. The manufacturer validates the device based on the public DAK and generates a second message that includes the HMAC and a manufacturer signature. The encrypted second message is communicated to the TEE circuitry. Upon receipt the TEE circuitry validates the AAIK data in the second message against the most recent AAIK and generates a third message that includes the HMAC, the original AAIK, the RHK and the manufacturer attestation. The AAIK thus remains unknown to both the current owner and the manufacturer.

公开(公告)号：US20210286594A1

公开(公告)日：2021-09-16

申请号：US16849103

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US20190319802A1

公开(公告)日：2019-10-17

申请号：US16456004

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： RAFAEL MISOCZKI ,  Santosh Ghosh ,  Manoj Sastry ,  David Wheeler

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/00

Abstract: In one example an apparatus comprises a computer readable memory to store a public key associated with a signing device, communication logic to receive, from the signing device, a signature chunk which is a component of a signature generated by a hash-based signature algorithm, and at least a first intermediate node value associated with the signature chunk, verification logic to execute a first hash chain beginning with the signature chunk to produce at least a first computed intermediate node value, execute a second hash chain beginning with the at least one intermediate node value associated with the signature chunk to produce a first computed final node value, and use the first computed intermediate node value and the first computed final computed node value to validate the signature generated by the hash-based signature algorithm. Other examples may be described.

公开(公告)号：US09043615B2

公开(公告)日：2015-05-26

申请号：US14196249

申请日：2014-03-04

Applicant: Intel Corporation

Inventor： Mark Fullerton ,  Moinul Khan ,  David Wheeler ,  John Brizek ,  Anitha Kona

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/57 ,  G06F21/72

CPC classification number: G06F12/1408 ,  G06F21/57 ,  G06F21/72 ,  G06F2221/2105

Abstract: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

Abstract translation: 在一个实施例中，一种装置包括无线装置内的密码处理器。 密码处理器包括至少一个加密单元。 密码处理器还包括用于存储一个或多个微代码指令的非易失性存储器，其中所述一个或多个微代码指令中的至少一个与敏感操作相关。 密码处理器还包括控制器，用于控制由至少一个密码单元执行一个或多个微代码指令，其中如果该设备处于不可信状态，则控制器将阻止执行敏感操作。