公开(公告)号：US11190335B2

公开(公告)日：2021-11-30

申请号：US15878348

申请日：2018-01-23

Applicant: Intel Corporation

Inventor： Boon Hong Oh ,  Ivan Fu Sun Teh ,  Chee Seng Tan

IPC: H04L7/06 ,  H04L29/06 ,  H04L7/00 ,  H04L7/04

Abstract: A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.

公开(公告)号：US20210286594A1

公开(公告)日：2021-09-16

申请号：US16849103

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US12075114B2

公开(公告)日：2024-08-27

申请号：US16729028

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Boon Hong Oh ,  Yeong Liang Low ,  Laila Ahmed Saad Ahmed Ahmed

IPC: H04N21/4367 ,  H04N5/05 ,  H04N21/23

CPC classification number: H04N21/4367 ,  H04N5/05 ,  H04N21/23

Abstract: A method for an audiovisual receiver to request an audiovisual transmitter to reset a communication link includes requesting the reset when the audiovisual receiver determines that the communication link is unlocked. The communication is determined to be unlocked when the active geometry of successive audiovisual frames transmitted from the transmitter to the receiver is determined by the receiver to be inconsistent. The communication is also determined to be unlocked when the interval between control bits of the successive audiovisual frames is inconsistent. When one or both of the inconsistencies is determined, the receiver sets an error bit in a register of the receiver that is accessible by the transmitter to determine from the receiver that the communication link is unlocked.

公开(公告)号：US11567733B2

公开(公告)日：2023-01-31

申请号：US16849103

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US20220100475A1

公开(公告)日：2022-03-31

申请号：US17541247

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US20190280850A1

公开(公告)日：2019-09-12

申请号：US16424071

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Chee Seng Tan ,  Boon Hong Oh ,  Ivan Fu Sun Teh

IPC: H04L7/00 ,  H04L7/04

Abstract: A receiver circuit includes a transition density detector circuit that generates a transition density signal based on a comparison between a transition density of data words to a transition density threshold. The receiver circuit also includes a bit shift and pattern detector circuit that bit shifts one of the data words to generate bit shifted data in response to the transition density signal indicating that the transition density of the data words has reached the transition density threshold. The bit shift and pattern detector circuit counts a number of bits shifts performed on the bit shifted data to locate a synchronization character. The receiver circuit also includes a word alignment circuit that bit shifts the data words by the number of bits shifts to generate word aligned data.