公开(公告)号：US11663452B2

公开(公告)日：2023-05-30

申请号：US16583217

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram Krishnamurthy ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Deepak Vinayak Kadetotad

IPC: G06F17/16 ,  G06N3/063 ,  G06F7/544 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06F17/16 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.