公开(公告)号：US20200006501A1

公开(公告)日：2020-01-02

申请号：US16490504

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Sean T. Ma ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Cheng-Ying Huang ,  Dewey Gilbert ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8252

Abstract: Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member.