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公开(公告)号:US20210091075A1
公开(公告)日:2021-03-25
申请号:US16579055
申请日:2019-09-23
Applicant: Intel Corporation
Inventor: Szuya S. LIAO , Scott B. CLENDENNING , Jessica TORRES , Lukas BAUMGARTEL , Kiran CHIKKADI , Diane LANCASTER , Matthew V. METZ , Florian GSTREIN , Martin M. MITAN , Rami HOURANI
IPC: H01L27/088 , H01L29/423
Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
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公开(公告)号:US20240088143A1
公开(公告)日:2024-03-14
申请号:US18516595
申请日:2023-11-21
Applicant: Intel Corporation
Inventor: Szuya S. Liao , Scott B. CLENDENNING , Jessica TORRES , Lukas BAUMGARTEL , Kiran CHIKKADI , Diane LANCASTER , Matthew V. METZ , Florian GSTREIN , Martin M. MITAN , Rami HOURANI
IPC: H01L27/088 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L23/538 , H01L27/092
CPC classification number: H01L27/0886 , H01L21/76229 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L23/5384 , H01L23/5389 , H01L27/0924 , H01L21/823462 , H01L21/823871
Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
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