公开(公告)号：US20210091075A1

公开(公告)日：2021-03-25

申请号：US16579055

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Scott B. CLENDENNING ,  Jessica TORRES ,  Lukas BAUMGARTEL ,  Kiran CHIKKADI ,  Diane LANCASTER ,  Matthew V. METZ ,  Florian GSTREIN ,  Martin M. MITAN ,  Rami HOURANI

IPC: H01L27/088 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20180219080A1

公开(公告)日：2018-08-02

申请号：US15506101

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Scott B. CLENDENNING ,  Szuya S. LIAO ,  Florian GSTREIN ,  Rami HOURANI ,  Patricio E. ROMERO ,  Grant M. KLOSTER ,  Martin M. MITAN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28247 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US20240088143A1

公开(公告)日：2024-03-14

申请号：US18516595

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Scott B. CLENDENNING ,  Jessica TORRES ,  Lukas BAUMGARTEL ,  Kiran CHIKKADI ,  Diane LANCASTER ,  Matthew V. METZ ,  Florian GSTREIN ,  Martin M. MITAN ,  Rami HOURANI

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/538 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5384 ,  H01L23/5389 ,  H01L27/0924 ,  H01L21/823462 ,  H01L21/823871

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20200287022A1

公开(公告)日：2020-09-10

申请号：US16881549

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Scott B. CLENDENNING ,  Martin M. MITAN ,  Szuya S. LIAO

IPC: H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

公开(公告)号：US20210408239A1

公开(公告)日：2021-12-30

申请号：US16913848

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Ashish AGRAWAL ,  Seung Hoon SUNG ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Willy RACHMADY ,  Jessica TORRES ,  Martin M. MITAN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of semiconductor channels with a first end and second end. In an embodiment, individual ones of the semiconductor channels comprise a nitrided surface. In an embodiment, the semiconductor device further comprises a source region at the first end of the stack and a drain region at the second end of the stack. In an embodiment, a gate dielectric surrounds the semiconductor channels, and a gate electrode surrounding the gate dielectric.

公开(公告)号：US20180226490A1

公开(公告)日：2018-08-09

申请号：US15750158

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Van H. LE ,  Scott B. CLENDENNING ,  Martin M. MITAN ,  Szuya S. LIAO

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

公开(公告)号：US20180130707A1

公开(公告)日：2018-05-10

申请号：US15573108

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Scott B. CLENDENNING ,  Martin M. MITAN ,  Timothy E. GLASSMAN ,  Flavio GRIGGIO ,  Grant M. KLOSTER ,  Kent N. FRASURE ,  Florian GSTREIN ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76876 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2221/1063

Abstract: Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.