公开(公告)号：US20220416998A1

公开(公告)日：2022-12-29

申请号：US17356168

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Dumitru-Daniel Dinu ,  Joseph Friel ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/06 ,  G06F21/72 ,  H04L9/00

Abstract: In one example an apparatus comprises an input state register, and a first round secure hash algorithm (SHA) datapath circuit communicatively coupled to the input state register and a second round secure hash algorithm (SHA) datapath circuit communicatively coupled to the first round secure hash datapath circuit, the first round secure has algorithm (SHA) datapath circuit and the second round secure hash algorithm (SHA) datapath circuit each comprising a first section to perform a θ step of a SHA calculation, a second section to perform a ρ step calculation, a third section to perform a π step of the SHA calculation, a fourth section to perform a χ step of the SHA calculation, and a fifth section to perform a ι step of the SHA calculation.

公开(公告)号：US12058261B2

公开(公告)日：2024-08-06

申请号：US17480360

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Dumitru-Daniel Dinu ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/30 ,  G06F17/14 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/3093 ,  H04L9/0869 ,  H04L9/3026 ,  H04L9/3247

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.

公开(公告)号：US20220006630A1

公开(公告)日：2022-01-06

申请号：US17480360

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Dumitru-Daniel Dinu ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/30 ,  H04L9/32 ,  H04L9/08

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.

公开(公告)号：US20220150046A1

公开(公告)日：2022-05-12

申请号：US17477028

申请日：2021-09-16

Applicant: Intel Corporation

Inventor： Dumitru-Daniel Dinu ,  Emre Karabulut ,  Aditya Katragada ,  Geoffrey Strongin ,  Avinash L. Varna

IPC: H04L9/00 ,  G06F21/72

Abstract: A security processor includes a scheduler to read input data blocks from an input buffer, send the input data blocks to one or more cryptographic circuits in a first random order; and send data blocks having random values in a second random order to one or more of the cryptographic circuits that did not receive the input data blocks.

公开(公告)号：US20220006611A1

公开(公告)日：2022-01-06

申请号：US17480413

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Dumitru-Daniel Dinu ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/00 ,  G06F7/72

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform an incomplete number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format, the plurality of compute nodes comprising at least a first NTT circuit comprising a single butterfly circuit to perform a series of butterfly calculations on input data; and a randomizing circuitry to randomize an order of the series of butterfly calculations.