公开(公告)号：US11275998B2

公开(公告)日：2022-03-15

申请号：US15994930

申请日：2018-05-31

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Sudarshan Srinivasan ,  Gregg William Baeckler ,  Duncan Moss ,  Sasikanth Avancha ,  Dipankar Das

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06F17/16 ,  G06F7/501 ,  G06F5/01 ,  G06F7/509 ,  H03M7/40 ,  H03M7/42 ,  H03M7/30

Abstract: The present disclosure relates generally to techniques for improving the implementation of certain operations on an integrated circuit. In particular, deep learning techniques, which may use a deep neural network (DNN) topology, may be implemented more efficiently using low-precision weights and activation values by efficiently performing down conversion of data to a lower precision and by preventing data overflow during suitable computations. Further, by more efficiently mapping multipliers to programmable logic on the integrated circuit device, the resources used by the DNN topology to perform, for example, inference tasks may be reduced, resulting in improved integrated circuit operating speeds.

公开(公告)号：US20190042939A1

公开(公告)日：2019-02-07

申请号：US15994930

申请日：2018-05-31

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Sudarshan Srinivasan ,  Gregg William Baeckler ,  Duncan Moss ,  Sasikanth Avancha ,  Dipankar Das

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06F5/01 ,  G06F17/16 ,  G06F7/501

Abstract: The present disclosure relates generally to techniques for improving the implementation of certain operations on an integrated circuit. In particular, deep learning techniques, which may use a deep neural network (DNN) topology, may be implemented more efficiently using low-precision weights and activation values by efficiently performing down conversion of data to a lower precision and by preventing data overflow during suitable computations. Further, by more efficiently mapping multipliers to programmable logic on the integrated circuit device, the resources used by the DNN topology to perform, for example, inference tasks may be reduced, resulting in improved integrated circuit operating speeds.