公开(公告)号：US20170346596A1

公开(公告)日：2017-11-30

申请号：US15166871

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Nathaniel L. Desimone ,  Theodore Zale Schoenborn ,  Earl Jeffrey Wight ,  Bryan Spry ,  Jorge Garcia Forteza ,  Sean Robert Graham ,  Duane Heller

IPC: H04L1/00 ,  G06F11/30 ,  G06F13/42 ,  H04L12/26

CPC classification number: H04L1/0034 ,  G06F11/221 ,  G06F11/24 ,  G06F11/3051 ,  G06F11/3062 ,  G06F13/4282 ,  H04L25/03885 ,  H04L43/087

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses to determine transmission equalization coefficients (TxEQs) for one or more lanes of a high speed serial link. Embodiments include determining a jitter tolerance for each TxEQ of a plurality of TxEQs for a lane of the link. The jitter tolerance for each TxEQ for the lane is based on a level of jitter induced on the lane to detect a number of errors on the lane; determining a voltage (VOC) margin for each TxEQ for the lane, wherein the voltage margin for the lane is based on a voltage corners test applied to the lane to detect a number of errors on the lane at a high voltage point and a low voltage point; determining a TxEQ that provides maximum jitter tolerance and based on the determined lowest voltage margin; and using the TxEQ for the lane during operation.