公开(公告)号：US11669146B2

公开(公告)日：2023-06-06

申请号：US17705445

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Efraim Rotem ,  Eliezer Weissman ,  Yoni Aizik ,  Daniel D. Lederman

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3206

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3296

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：US20250004536A1

公开(公告)日：2025-01-02

申请号：US18216456

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ankush Varma ,  Nilanjan Palit ,  Yuval Bustan ,  Eran Barnett ,  Eliezer Weissman ,  Stanley Chen ,  Arjan Van De Ven

IPC: G06F1/3296 ,  G06F1/324

Abstract: Techniques and mechanisms for determining operation a processor core which is in a common power delivery domain with one or more other processor cores. In an embodiment, an execution of instructions by a first core of a processor module is selectively throttled based on the detection of a single violation condition. The throttling is performed while the cores of the processor module are each maintained in a current power state. The single violation condition comprises a violation of a test criteria by the first core, while the one or more other cores of the module each satisfy the test criteria. In the case of a multiple violation condition, each core of the processor module is transitioned from one power state to another power state. In another embodiment, the test criteria includes or is otherwise based on a threshold level of a dynamic capacitance for a given core.