公开(公告)号：US20230305960A1

公开(公告)日：2023-09-28

申请号：US17705015

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Oz Shitrit ,  Elyada Bar-Chaim ,  Mauricio Valverde Monge ,  Ayan Mandal

IPC: G06F12/0815

CPC classification number: G06F12/0815

Abstract: Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.