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公开(公告)号:US09947388B2
公开(公告)日:2018-04-17
申请号:US15072278
申请日:2016-03-16
Applicant: Intel Corporation
Inventor: Jaydeep P. Kulkarni , Iqbal R. Rajwani , Eric K. Donkoh
IPC: G11C7/22 , G11C11/419
CPC classification number: G11C11/419
Abstract: Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.
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公开(公告)号:US20170270998A1
公开(公告)日:2017-09-21
申请号:US15072278
申请日:2016-03-16
Applicant: Intel Corporation
Inventor: Jaydeep P. Kulkarni , Iqbal R. Rajwani , Eric K. Donkoh
IPC: G11C11/419
CPC classification number: G11C11/419
Abstract: Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.
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