公开(公告)号：US20240028577A1

公开(公告)日：2024-01-25

申请号：US18225939

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Jixing Gu ,  Vinodh Gopal ,  Fang Xie ,  David Cohen ,  Wajdi Feghali

IPC: G06F16/22

CPC classification number: G06F16/2272 ,  G06F16/24568

Abstract: An apparatus may include an accelerator and a processor. The processor may receive an input string targeting a data buffer comprising a plurality of strings. The processor may receive, from the accelerator, a fixed-length data buffer based on the data buffer, respective ones of a plurality of entries of the fixed-length data buffer based on respective ones of the strings. The processor may receive, from the accelerator, a plurality of streams, respective ones of the plurality of streams to comprise a portion of respective entries in the fixed-length data buffer. The processor may generate, based on the input string, a plurality of target portions of the input string. The processor may receive, from the accelerator, indexes of the plurality of streams based on respective target portions of the input string matching respective entries of the plurality of streams. The processor may aggregate the indexes received from the accelerator.