公开(公告)号：US20240333940A1

公开(公告)日：2024-10-03

申请号：US18128747

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Phoenix WORTH ,  Faouzi KOSSENTINI ,  Foued BEN AMARA

IPC: H04N19/146

CPC classification number: H04N19/146

Abstract: A system that includes at least one memory and circuitry coupled to the at least one memory, wherein the circuitry is to access media from the at least one memory, wherein the circuitry is to: select one or more settings to apply to encode the video based on a cost of signaling applicable settings.

公开(公告)号：US20190045210A1

公开(公告)日：2019-02-07

申请号：US15898022

申请日：2018-02-15

Applicant: Intel Corporation

Inventor： Hassen GUERMAZI ,  Nader MAHDI ,  Chekib NOUIRA ,  Omar KHLIF ,  Faouzi KOSSENTINI ,  Foued BEN AMARA

IPC: H04N19/51 ,  H04N19/176 ,  H04N19/159 ,  H04N19/46

Abstract: Techniques related to video encoding are discussed that, for each block of input video, select an individual partitioning and coding mode selection technique from multiple such selection techniques. For a picture, the selection algorithm takes as input scores for individual blocks, costs of the various partitioning and coding mode selection techniques, and various detector outputs. The selection algorithm provides as output a partitioning and coding mode selection technique for each block in picture. The algorithms selection is such that the overall cost of the selected algorithms in the picture is as close as possible to a given picture budget. Furthermore, a partitioning and coding mode selection algorithms, binary depth partitioning (BDP), is discussed. For a block, BDP provides fast convergence to a partitioning and associated coding modes first evaluating intermediate partitioning options and converging on the final partitioning by evaluating either larger of smaller partitions.