公开(公告)号：US20220100680A1

公开(公告)日：2022-03-31

申请号：US17033728

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： GEORGE CHRYSOS ,  BHARGAVI NARAYANASETTY ,  JESUS CORBAL ,  CHING-KAI LIANG ,  CHINMAY ASHOK ,  FRANCIS TSENG

IPC: G06F13/16 ,  G06F13/40

Abstract: Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described. In one embodiment, a hardware accelerator includes a plurality of dataflow execution circuits that each comprise a register file, a plurality of execution circuits, and a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file, and the graph station circuit is to select for execution a first dataflow operation entry when its input operands are available, and clear ready fields of the input operands in the first dataflow operation entry when a result of the execution is stored in the register file; a cross dependence network coupled between the plurality of dataflow execution circuits to send data between the plurality of dataflow execution circuits according to a second dataflow operation entry; and a memory execution interface coupled between the plurality of dataflow execution circuits and a cache bank to send data between the plurality of dataflow execution circuits and the cache bank according to a third dataflow operation entry.