公开(公告)号：US20220206975A1

公开(公告)日：2022-06-30

申请号：US17134118

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  GEORGE POWLEY

IPC: G06F13/28 ,  H03M7/30

Abstract: Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.