公开(公告)号：US20190004726A1

公开(公告)日：2019-01-03

申请号：US15639450

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： PENG LI ,  JAWAD B. KHAN ,  SANJEEV N. TRIKA ,  VINODH GOPAL

IPC: G06F3/06

Abstract: One embodiment provides an apparatus. The apparatus include a device storage logic. The device storage logic is to determine a key-based pointer based, at least in part, on a key included in an input key-value (KV) pair received from a host device and to determine whether a unique input KV data block included in the input KV pair is duplicated in a nonvolatile memory circuitry of a storage device. The device storage logic is further to set a descriptor pointer associated with the unique input KV data block to point to a physical nonvolatile memory (NVM) address associated with an existing unique data block and increment a first reference count associated with the existing unique data block, if the unique input KV data block is a duplicate of the existing unique data block, or store the input KV data block to a physical NVM location associated with a selected physical NVM address, set the descriptor pointer to point to the selected physical NVM address and set a second reference count associated with the selected physical NVM address to one, if the unique input KV data block is not duplicated in the NVM circuitry.

公开(公告)号：US20180183900A1

公开(公告)日：2018-06-28

申请号：US15390579

申请日：2016-12-26

Applicant: Intel Corporation

Inventor： JAMES D. GUILFORD ,  VINODH GOPAL ,  DANIEL F. CUTTER

IPC: H04L29/06

CPC classification number: H04L69/04 ,  H04L69/12

Abstract: In an embodiment, a processor comprises a plurality of processing cores and a compression accelerator to compress an input stream comprising a first data block and a second data block. The compression accelerator comprises a first compression engine to compress the first data block; and a second compression engine to update state data for the second compression engine using a sub-portion of the first data block; and after an update of the state data for the second compression engine using the sub-portion of the first data block, compress a second data block using the updated state data for the second compression engine. Other embodiments are described and claimed.

公开(公告)号：US20160173123A1

公开(公告)日：2016-06-16

申请号：US14571658

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  GILBERT M. WOLRICH ,  DANIEL F. CUTTER

IPC: H03M7/40 ,  H03M7/30

CPC classification number: H03M7/40 ,  H03M7/3086 ,  H03M7/6011

Abstract: In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to: receive input data to be compressed; select a particular intermediate format of a plurality of intermediate formats based on a type of compression software to be executed by at least one of the plurality of hardware processing cores; perform a duplicate string elimination operation on the input data to generate a partially compressed output in the particular intermediate format; and provide the partially compressed output in the particular intermediate format to the compression software, wherein the compression software is to perform an encoding operation on the partially compressed output to generate a final compressed output. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括耦合到多个硬件处理核心的压缩加速器。 压缩加速器是：接收要压缩的输入数据; 基于由所述多个硬件处理核心中的至少一个执行的压缩软件的类型，选择多个中间格式的特定中间格式; 对输入数据执行重复字符串消除操作，以产生特定中间格式的部分压缩输出; 并将特定中间格式的部分压缩的输出提供给压缩软件，其中压缩软件将对部分压缩的输出执行编码操作以产生最终的压缩输出。 描述和要求保护其他实施例。

公开(公告)号：US20220206975A1

公开(公告)日：2022-06-30

申请号：US17134118

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  GEORGE POWLEY

IPC: G06F13/28 ,  H03M7/30

Abstract: Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.

公开(公告)号：US20180287630A1

公开(公告)日：2018-10-04

申请号：US15935117

申请日：2018-03-26

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  DANIEL F. CUTTER ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  H04L1/24

CPC classification number: H03M7/6041 ,  H03M7/3086 ,  H03M7/6005 ,  H03M7/6011 ,  H04L1/24

Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

公开(公告)号：US20160255100A1

公开(公告)日：2016-09-01

申请号：US15049519

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  CHRISTOPHER F. CLARK ,  GILBERT M. WOLRICH ,  WAJDI K. FEGHALI

IPC: H04L29/06 ,  G06F17/30

CPC classification number: H04L63/145 ,  G06F7/02 ,  G06F17/30949 ,  G06F17/30985 ,  G06F21/567 ,  G06F2207/025 ,  H04L63/0245 ,  H04L63/1416

Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

Abstract translation: 公开了对网络包检测进行字符串匹配的方法和装置。 在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。 每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。 如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。 可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。 切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配​​结果。

公开(公告)号：US20160173126A1

公开(公告)日：2016-06-16

申请号：US15053921

申请日：2016-02-25

Applicant: INTEL CORPORATION

Inventor： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDING OZTURK ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  G06F9/30

CPC classification number: H03M7/60 ,  G06F9/30029 ,  H03M7/3068 ,  H03M7/6058

Abstract: An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream. Other embodiments are described and claimed.

Abstract translation: 实施例可以包括可以执行压缩相关操作的电路，其可以包括：（a）至少部分地在数据结构中指示要被编码为的至少一个字符子集的至少一个位置 （b）至少部分比较至少一对具有相同预定固定大小的多字节数据字，（c）至少部分维持指向潜在匹配字符串的指针数组， 与至少一个当前检查的字符串进行比较，和/或（d）至少部分地分配第一缓冲器部分，以将来自要输入的压缩数据的至少一部分未压缩数据存储到要压缩的应用缓冲器中 产生压缩数据流。 描述和要求保护其他实施例。

公开(公告)号：US20210377356A1

公开(公告)日：2021-12-02

申请号：US16887087

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： FRANCESC GUIM BERNAT ,  KSHITIJ ARUN DOSHI ,  KENNETH SHOEMAKER ,  VINODH GOPAL ,  NED M. SMITH

IPC: H04L29/08 ,  H04L12/935 ,  H04L12/933 ,  H04L12/861 ,  H04L12/927

Abstract: In one embodiment, a method includes: receiving, in an edge platform, a plurality of messages from a plurality of edge devices coupled to the edge platform, the plurality of messages comprising metadata including priority information and granularity information; extracting at least the priority information from the plurality of messages; storing the plurality of messages in entries of a pending request queue according to the priority information; selecting a first message stored in the pending request queue for delivery to a destination circuit; and sending a message header for the first message to the destination circuit via at least one interface circuit, the message header including the priority information, and thereafter sending a plurality of packets including payload information of the first message to the destination circuit via the at least one interface circuit. Other embodiments are described and claimed.

公开(公告)号：US20180183462A1

公开(公告)日：2018-06-28

申请号：US15393190

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD

IPC: H03M7/40 ,  H03M7/30

CPC classification number: H03M7/40 ,  H03M7/02 ,  H03M7/30 ,  H03M7/3086 ,  H03M7/6023

Abstract: Techniques and apparatus for parallel decompression are described. In one embodiment, for example, an apparatus to provide parallel decompression may include at least one memory and logic for a decompression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine decompression information of a compressed data unit, annotate the compressed data unit with at least a portion of the decompression information to generate an annotated data unit, parallel-decode the annotated data unit to generate a plurality of intermediate elements, and decode and merge the plurality of intermediate elements to generate a decompressed data unit. Other embodiments are described and claimed.

公开(公告)号：US20170060584A1

公开(公告)日：2017-03-02

申请号：US15257833

申请日：2016-09-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。