公开(公告)号：US20160378442A1

公开(公告)日：2016-12-29

申请号：US14750635

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Jong Soo Park ,  Mikhail Smelyanskiy ,  Geoff Lowney

IPC: G06F9/45

CPC classification number: G06F8/41 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/4435 ,  G06F9/44521 ,  G06F17/16

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize sparse matrix execution. An example disclosed apparatus includes a context former to identify a matrix function call from a matrix function library, the matrix function call associated with a sparse matrix, a pattern matcher to identify an operational pattern associated with the matrix function call, and a code generator to associate a function data structure with the matrix function call exhibiting the operational pattern, the function data structure stored external to the matrix function library, and facilitate a runtime link between the function data structure and the matrix function call.

Abstract translation: 公开了方法，装置，系统和制品以优化稀疏矩阵执行。 一个示例公开的装置包括一个上下文变换器，用于从矩阵函数库识别矩阵函数调用，与稀疏矩阵相关联的矩阵函数调用，用于识别与矩阵函数调用相关联的操作模式的模式匹配器，以及代码生成器 将功能数据结构与表现操作模式的矩阵函数调用关联，存储在矩阵函数库外部的函数数据结构，并促进函数数据结构和矩阵函数调用之间的运行时链接。

公开(公告)号：US20190005175A1

公开(公告)日：2019-01-03

申请号：US15636265

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Xinmin Tian ,  Geoff Lowney

IPC: G06F17/50

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve FPGA pipeline emulation efficiency on CPUs. An example disclosed apparatus includes a loop detector to identify a register shift loop in field programmable gate array (FPGA) code, an unroller to shift and store pipeline stages in the register shift loop to a temporary unroll array, an intermediate canceller to cancel out intermediate load and store values of the temporary unroll array to retain last shifted values of the pipeline stages, and a propagator to improve emulation efficiency of the FPGA code by generating a scalar loop of the retained last shifted values for a vectorization input.

公开(公告)号：US09720663B2

公开(公告)日：2017-08-01

申请号：US14750635

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Jong Soo Park ,  Mikhail Smelyanskiy ,  Geoff Lowney

IPC: G06F9/45 ,  G06F9/445 ,  G06F17/16

CPC classification number: G06F8/41 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/4435 ,  G06F9/44521 ,  G06F17/16

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize sparse matrix execution. An example disclosed apparatus includes a context former to identify a matrix function call from a matrix function library, the matrix function call associated with a sparse matrix, a pattern matcher to identify an operational pattern associated with the matrix function call, and a code generator to associate a function data structure with the matrix function call exhibiting the operational pattern, the function data structure stored external to the matrix function library, and facilitate a runtime link between the function data structure and the matrix function call.

公开(公告)号：US20210326504A1

公开(公告)日：2021-10-21

申请号：US17134303

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Xinmin Tian ,  Geoff Lowney

IPC: G06F30/331

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve FPGA pipeline emulation efficiency on CPUs. An example disclosed apparatus includes a loop detector to identify a register shift loop in field programmable gate array (FPGA) code, an unroller to shift and store pipeline stages in the register shift loop to a temporary unroll array, an intermediate canceller to cancel out intermediate load and store values of the temporary unroll array to retain last shifted values of the pipeline stages, and a propagator to improve emulation efficiency of the FPGA code by generating a scalar loop of the retained last shifted values for a vectorization input.

公开(公告)号：US10909287B2

公开(公告)日：2021-02-02

申请号：US15636265

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Xinmin Tian ,  Geoff Lowney

IPC: G06F30/331

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve FPGA pipeline emulation efficiency on CPUs. An example disclosed apparatus includes a loop detector to identify a register shift loop in field programmable gate array (FPGA) code, an unroller to shift and store pipeline stages in the register shift loop to a temporary unroll array, an intermediate canceller to cancel out intermediate load and store values of the temporary unroll array to retain last shifted values of the pipeline stages, and a propagator to improve emulation efficiency of the FPGA code by generating a scalar loop of the retained last shifted values for a vectorization input.