公开(公告)号：US12124383B2

公开(公告)日：2024-10-22

申请号：US17862739

申请日：2022-07-12

申请人： Intel Corporation

发明人： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC分类号： G06F12/00 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/123 ,  G06T1/60

CPC分类号： G06F12/123 ,  G06F12/0875 ,  G06F12/0891 ,  G06T1/60 ,  G06F2212/302

摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US20210150663A1

公开(公告)日：2021-05-20

申请号：US17095590

申请日：2020-11-11

申请人： Intel Corporation

发明人： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC分类号： G06T1/60 ,  G06T1/20 ,  G06N5/04 ,  G06F12/0802

摘要： Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US20180181404A1

公开(公告)日：2018-06-28

申请号：US15391915

申请日：2016-12-28

申请人： Intel Corporation

发明人： Hideki Saito Ido ,  Eric N. Garcia ,  Xinmin Tian ,  Milind B. Girkar ,  James Brodman

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/30058 ,  G06F9/3806 ,  G06F15/76

摘要： In one example, a system for generating vector based selection control statements can include a processor to determine a vector cost of the selection control statement is below a scalar cost and determine the selection control statement is to be executed in a sorted order based on dependencies between branch instructions of the selection control statement. The processor can also determine a program ordering of labels of the selection control statement does not match a mathematical ordering of the labels and execute the selection control statement with a vector of values, wherein the selection control statement is to be executed based on a jump table and a sorted unique value technique, wherein the sorted unique value technique comprises selecting at least one of the plurality of branch instructions from the jump table.

公开(公告)号：US20240078630A1

公开(公告)日：2024-03-07

申请号：US18490593

申请日：2023-10-19

申请人： Intel Corporation

发明人： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC分类号： G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20

CPC分类号： G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20 ,  G06F2212/251

摘要： Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US20220156202A1

公开(公告)日：2022-05-19

申请号：US17590362

申请日：2022-02-01

申请人： Intel Corporation

发明人： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC分类号： G06F12/123 ,  G06F12/0891 ,  G06T1/60 ,  G06F12/0875

摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US10776093B2

公开(公告)日：2020-09-15

申请号：US16304644

申请日：2016-07-01

申请人： Intel Corporation

发明人： Mikhail Plotnikov ,  Hideki Ido ,  Xinmin Tian ,  Sergey Preis ,  Milind B. Girkar ,  Maxim Shutov

IPC分类号： G06F9/44 ,  G06F8/41

摘要： Methods, apparatus, and system to optimize compilation of source code into vectorized compiled code, notwithstanding the presence of output dependencies which might otherwise preclude vectorization.

公开(公告)号：US10459858B2

公开(公告)日：2019-10-29

申请号：US15804939

申请日：2017-11-06

申请人： INTEL CORPORATION

发明人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John P. Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry H. Wang ,  Piyush N. Desai

IPC分类号： G06F9/38 ,  G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F11/34 ,  G06F11/30 ,  G06F12/0875

摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US09069605B2

公开(公告)日：2015-06-30

申请号：US14067223

申请日：2013-10-30

申请人： Intel Corporation

发明人： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

IPC分类号： G06F9/46 ,  G06F9/48

CPC分类号： G06F9/4843

摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

摘要翻译： 方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的顺控程序上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。

公开(公告)号：US20220350751A1

公开(公告)日：2022-11-03

申请号：US17862739

申请日：2022-07-12

申请人： Intel Corporation

发明人： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC分类号： G06F12/123 ,  G06F12/0875 ,  G06F12/0891 ,  G06T1/60

摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US20220114108A1

公开(公告)日：2022-04-14

申请号：US17428529

申请日：2020-03-14

申请人： Intel Corporation

发明人： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K. ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC分类号： G06F12/123 ,  G06F12/0891 ,  G06F12/0875 ,  G06T1/60

摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.