公开(公告)号：US09697094B2

公开(公告)日：2017-07-04

申请号：US14672131

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Debaleena Das ,  George H Huang ,  Jing Ling ,  Reza E Daftari ,  Meera Ganesan

IPC: G06F11/00 ,  G06F11/16 ,  G06F3/06 ,  G06F11/20

CPC classification number: G06F11/1662 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/1004 ,  G06F11/108 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2094 ,  G06F2201/825

Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.