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公开(公告)号：US20190089373A1
公开(公告)日：2019-03-21
申请号：US16196422
申请日：2018-11-20
Applicant: Intel Corporation
Inventor： Gert Schedelbeck , Stefan Uhlemann
Abstract: A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.
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公开(公告)号：US11750290B2
公开(公告)日：2023-09-05
申请号：US17117206
申请日：2020-12-10
Applicant: Intel Corporation
Inventor： Rainer Strobel , Gert Schedelbeck
CPC classification number: H04B10/27 , H04L1/004 , H04L7/0075
Abstract: An optical network receiver (ONU) circuit associated with a passive optical network (PON) is disclosed. The ONU circuit comprises one or more processors is configured to operate in a hunt state, wherein the one or more processors is configured to detect frame boundaries associated with an incoming data signal based on a detecting a predefined synchronization (psync) pattern associated with the incoming data signal and transition to a pre-sync state, when the predefined psync pattern is detected correctly. The one or more processors is further configured to operate in the pre-sync state, wherein the one or more processors is configured to perform forward error correction (FEC) decoding for the incoming data signal, in order to determine signal statistics associated with the incoming data signal.
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