公开(公告)号：US11010058B2

公开(公告)日：2021-05-18

申请号：US16436917

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damaria ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.