公开(公告)号：US10707121B2

公开(公告)日：2020-07-07

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Mark A. Levan ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao

IPC: H01L21/768 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11548 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

公开(公告)号：US10318170B2

公开(公告)日：2019-06-11

申请号：US15860540

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G11C16/06 ,  G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US10134758B2

公开(公告)日：2018-11-20

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/768 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US20180130819A1

公开(公告)日：2018-05-10

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L21/768 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US09857989B1

公开(公告)日：2018-01-02

申请号：US15283296

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G11C16/06 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.

公开(公告)号：US09741734B2

公开(公告)日：2017-08-22

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US11010058B2

公开(公告)日：2021-05-18

申请号：US16436917

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damaria ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US20180307412A1

公开(公告)日：2018-10-25

申请号：US15860540

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US20180190540A1

公开(公告)日：2018-07-05

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao ,  Mark A. Levan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

公开(公告)号：US20170170190A1

公开(公告)日：2017-06-15

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  H01L21/768 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.