公开(公告)号：US20210051149A1

公开(公告)日：2021-02-18

申请号：US17084406

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Barry E. HUNTLEY ,  Gilbert NEIGER ,  H. Peter ANVIN ,  Asit K. MALLICK ,  Adriaan VAN DE VEN ,  Scott D. RODGERS

IPC: H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US20230281016A1

公开(公告)日：2023-09-07

申请号：US17712116

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Gilbert NEIGER ,  H. Peter ANVIN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/3806

Abstract: Techniques for flexible return and event delivery are described. In particular, in some examples, event delivery causes a stack switch if the event stack level is greater than the current stack level wherein the new stack level is always the greater of the current stack level and the event stack level.

公开(公告)号：US20220171625A1

公开(公告)日：2022-06-02

申请号：US17590648

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Gilbert NEIGER ,  Deepak K. GUPTA ,  H. Peter ANVIN

IPC: G06F9/30 ,  G06F21/52

Abstract: An apparatus and method for efficiently managing shadow stacks. For example, one embodiment of a processor comprises: a plurality of registers to store a plurality of shadow stack pointers (SSPs); event processing circuitry to select a first SSP of the plurality of SSPs from a first register of the plurality of registers responsive to receipt of a first event associated with a first event priority level, the first SSP usable to identify a top of a first shadow stack; verification and utilization checking circuitry to determine whether the first SSP has been previously verified, wherein if the first SSP has not been previously verified then initiating a set of atomic operations to verify the first SSP and confirm that the first SSP is not in use, the set of atomic operations using a locking operation to lock data until the set of atomic operations are complete.

公开(公告)号：US20210303304A1

公开(公告)日：2021-09-30

申请号：US16833599

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOQUE ,  Gilbert NEIGER ,  Deepak K. GUPTA ,  H. Peter ANVIN

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/54 ,  G06F16/176

Abstract: An apparatus and method for efficiently managing shadow stacks. For example, one embodiment of a processor comprises: a plurality of registers to store a plurality of shadow stack pointers (SSPs), each SSP associated with a different event priority; event processing circuitry to select a first SSP of the plurality of SSPs from a first register of the plurality of registers responsive to receipt of a first event associated with a first event priority level, the first SSP usable to identify a top of a first shadow stack; verification and utilization checking circuitry to determine whether the first SSP has been previously verified, wherein if the first SSP has not been previously verified then initiating a set of atomic operations to verify the first SSP and confirm that the first SSP is not in use, the set of atomic operations using a locking operation to lock data until the set of atomic operations are complete, and wherein if the first SSP has been previously verified, then re-verifying the first SSP and confirming that the first SSP is not in use without using the locking operation.

公开(公告)号：US20210258311A1

公开(公告)日：2021-08-19

申请号：US17307992

申请日：2021-05-04

Applicant: Intel Corporation

Inventor： Barry E. HUNTLEY ,  Gilbert NEIGER ,  H. Peter ANVIN ,  Asit K. MALLICK ,  Adriaan VAN DE VEN ,  Scott D. RODGERS

IPC: H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US20190089709A1

公开(公告)日：2019-03-21

申请号：US16194648

申请日：2018-11-19

Applicant: Intel Corporation

Inventor： Barry E. HUNTLEY ,  Gilbert NEIGER ,  H. Peter ANVIN ,  Asit K. MALLICK ,  Adriaan VAN DE VEN ,  Scott D. RODGERS

IPC: H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.