公开(公告)号：US20250113581A1

公开(公告)日：2025-04-03

申请号：US18374599

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Hwichan JUN ,  Guillaume BOUCHE ,  Sudipto NASKAR

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Trench contact structures with airgap spacers, and methods of fabricating trench contact structures with airgap spacers, are described. In an example, an integrated circuit structure includes a fin structure or a nanowire structure. An epitaxial source or drain structure is on the fin structure or the nanowire structure. A gate structure is over the fin structure or around the nanowire structure. A trench contact structure is laterally spaced apart from the gate structure and coupled to the epitaxial source or drain structure. A trench contact spacer is adjacent to sidewalls of the trench contact structure, the trench contact spacer including an outer spacer portion, an airgap, and an inner spacer portion.

公开(公告)号：US20250112150A1

公开(公告)日：2025-04-03

申请号：US18375077

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Hwichan JUN ,  Lee ROCKFORD

IPC: H01L23/528 ,  H01L23/544 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Structures having registration marks for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer comprising a plurality of nanowire-based or fin-based transistors and a pad laterally adjacent to the plurality of nanowire-based or fin-based transistors, the pad having first grating structures aligned along an X-direction and second grating structures aligned along a Y-direction therein, the first and second grating structures exposed at a backside surface of the front side structure. The front-side also includes a plurality of metallization layers above the plurality of nanowire-based or fin-based transistors. The integrated circuit structure also includes a backside structure below the plurality of nanowire-based or fin-based transistors of the device layer of the front side structure, the backside structure comprising backside metal layers and vias.