公开(公告)号：US20180349544A1

公开(公告)日：2018-12-06

申请号：US15610223

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Mahesh A. Iyer ,  Ian Milton ,  Dai Le

IPC: G06F17/50

Abstract: An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform retiming for the circuit design, where registers are moved across one or more portions of the combinational logic. The registers may be retimed while considering hybrid initial states of the registers. At least some of the registers may have don't-care initial states. When performing backward retiming, initial states of the retimed registers may be computed that is consistent with the original initial state and functionality of the combinational logic while maximizing the number of don't-care initial states. When performing forward retiming across non-justifiable combinational elements, any don't-care initial states may be assumed to be equal to a deterministic binary value, and the initial states of the retimed registers may be computed that is consistent with the original initial states and functionality of the combinational logic.