公开(公告)号：US20160299761A1

公开(公告)日：2016-10-13

申请号：US15181374

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： BRET L. TOLL ,  JASON W. BRANDT ,  JOHN G. HOLM

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/3009 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/46 ,  G06F15/80

Abstract: Methods and apparatuses relating to a common architectural state presentation for a processor having cores of different types are described. In one embodiment, a processor includes a first core, a second core, wherein the first core comprises a unique architectural state and a common architectural state with the second core, and circuitry to migrate a thread from said first core to said second core, said circuitry to migrate the common architectural state from the first core to the second core, and migrate the unique architectural state to a storage external from the second core

Abstract translation: 描述与具有不同类型的核的处理器的公共架构状态呈现有关的方法和装置。 在一个实施例中，处理器包括第一核心，第二核心，其中所述第一核心包括独特的架构状态和与所述第二核心的共同架构状态，以及将线程从所述第一核心迁移到所述第二核心的电路， 将公共架构状态从第一核心迁移到第二核心的电路，并将独特架构状态迁移到从第二核心外部的存储器

公开(公告)号：US20190205201A1

公开(公告)日：2019-07-04

申请号：US15857376

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： SUBHANKAR PANDA ,  GAURAV PORWAL ,  JOHN G. HOLM

IPC: G06F11/07

Abstract: An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.