公开(公告)号：US20210240475A1

公开(公告)日：2021-08-05

申请号：US17124813

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  MARK CHARNEY ,  MICHAEL MISHAELI ,  ROBERT VALENTINE ,  ITAI RAVID ,  JASON W. BRANDT ,  GILBERT NEIGER ,  BARUCH CHAIKIN ,  EFRAIM ROTEM

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20160299761A1

公开(公告)日：2016-10-13

申请号：US15181374

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： BRET L. TOLL ,  JASON W. BRANDT ,  JOHN G. HOLM

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/3009 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/46 ,  G06F15/80

Abstract: Methods and apparatuses relating to a common architectural state presentation for a processor having cores of different types are described. In one embodiment, a processor includes a first core, a second core, wherein the first core comprises a unique architectural state and a common architectural state with the second core, and circuitry to migrate a thread from said first core to said second core, said circuitry to migrate the common architectural state from the first core to the second core, and migrate the unique architectural state to a storage external from the second core

Abstract translation: 描述与具有不同类型的核的处理器的公共架构状态呈现有关的方法和装置。 在一个实施例中，处理器包括第一核心，第二核心，其中所述第一核心包括独特的架构状态和与所述第二核心的共同架构状态，以及将线程从所述第一核心迁移到所述第二核心的电路， 将公共架构状态从第一核心迁移到第二核心的电路，并将独特架构状态迁移到从第二核心外部的存储器

公开(公告)号：US20230376252A1

公开(公告)日：2023-11-23

申请号：US18200544

申请日：2023-05-22

Applicant: Intel Corporation

Inventor： VEDVYAS SHANBHOGUE ,  JASON W. BRANDT ,  RAVI L. SAHITA ,  BARRY E. HUNTLEY ,  BAIJU V. PATEL

IPC: G06F3/06 ,  G06F9/30 ,  G06F21/52 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1036

CPC classification number: G06F3/0673 ,  G06F9/30145 ,  G06F3/0622 ,  G06F3/0629 ,  G06F21/52 ,  G06F9/3861 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/30134 ,  G06F12/1009 ,  G06F9/30101 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1063 ,  G06F12/1491 ,  G06F12/1036 ,  G06F2212/651 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/657

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20210406019A1

公开(公告)日：2021-12-30

申请号：US16914343

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： TOBY OPFERMAN ,  PRASHANT SETHI ,  ABHIMANYU K. VARDE ,  BARRY E. HUNTLEY ,  MICHAEL W. Chynoweth ,  JASON W. BRANDT

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to an instruction for operating system transparent instruction state management of new instructions for application threads are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, and an execution circuit to execute the decoded single instruction to cause a context switch from a current state to a state comprising additional state data that is not supported by an execution environment of an operating system that executes on the hardware processor.

公开(公告)号：US20170102947A1

公开(公告)日：2017-04-13

申请号：US15384300

申请日：2016-12-19

Applicant: INTEL CORPORATION

Inventor： TOBY OPFERMAN ,  JAMES B. CROSSLAND ,  JASON W. BRANDT ,  BEEMAN C. STRONG

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/30123 ,  G06F9/30145 ,  G06F9/3877 ,  G06F11/3024 ,  G06F11/3079 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F11/36 ,  G06F11/3636 ,  G06F11/3656

Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

公开(公告)号：US20210109684A1

公开(公告)日：2021-04-15

申请号：US17131731

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： VEDVYAS SHANBHOGUE ,  JASON W. BRANDT ,  RAVI L. SAHITA ,  BARRY E. HUNTLEY ,  BAIJU V. PATEL

IPC: G06F3/06 ,  G06F9/30 ,  G06F21/52 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1036

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20160381050A1

公开(公告)日：2016-12-29

申请号：US14752221

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： VEDVYAS SHANBHOGUE ,  JASON W. BRANDT ,  RAVI L. SAHITA ,  BARRY E. HUNTLEY ,  BAIJU V. PATEL

IPC: H04L29/06 ,  G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0673 ,  G06F3/0622 ,  G06F3/0629 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/3861 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1063 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/1491 ,  G06F21/52 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.

Abstract translation: 方面的处理器包括解码指令的解码单元。 处理器还包括与解码单元耦合的执行单元。 执行单元响应于该指令，是确定由于指令而尝试改变影子栈的影子堆栈指针将导致阴影堆栈指针超过允许的范围。 响应于确定对阴影堆栈指针的尝试改变将导致阴影堆栈指针超过允许的范围，执行单元也将采取异常。 公开了其他处理器，方法，系统和指令。

公开(公告)号：US20160170820A1

公开(公告)日：2016-06-16

申请号：US14566374

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： BEEMAN C. STRONG ,  STEPHEN J. ROBINSON ,  JASON W. BRANDT ,  PETER LACHNER

IPC: G06F11/07 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F9/30 ,  G06F11/3636

Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.

Abstract translation: 公开了一种在调试跟踪架构中实现跟踪延迟数据分组的处理设备。 处理装置是确定与执行指令相对应的顺序相对于执行指令序列中的指令类型的其他执行指令的顺序，识别对应于第一分组类型的第一数据分组，并依次 根据订单编号对数据跟踪日志中的第一分组类型的数据分组进行排序，识别与第二分组类型对应的第二数据分组，并根据订单号对数据分组进行顺序排序 的数据跟踪日志中的第二分组类型，并将所识别的第一和第二数据分组映射到指令，其中在指令的退休之后生成第一或第二数据分组中的至少一个。

公开(公告)号：US20230350687A1

公开(公告)日：2023-11-02

申请号：US18143513

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： ROBERT S. CHAPPELL ,  JASON W. BRANDT ,  ALAN COX ,  ASIT MALLICK ,  JOSEPH NUZMAN ,  ARJAN VAN DE VEN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

CPC classification number: G06F9/3842 ,  G06F9/30145 ,  G06F21/556 ,  G06F9/30058 ,  G06F2221/033

Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

公开(公告)号：US20230076318A1

公开(公告)日：2023-03-09

申请号：US17903307

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  MARK CHARNEY ,  MICHAEL MISHAELI ,  ROBERT VALENTINE ,  ITAI RAVID ,  JASON W. BRANDT ,  GILBERT NEIGER ,  BARUCH CHAIKIN ,  EFRAIM ROTEM

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.