公开(公告)号：US10482372B2

公开(公告)日：2019-11-19

申请号：US14757397

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Jae-Sun Seo

IPC: G06N3/04 ,  G06N3/02 ,  G06N3/063 ,  G06F13/42

Abstract: Systems and methods for an interconnection scheme for reconfigurable neuromorphic hardware are disclosed. A neuromorphic processor may include a plurality of corelets, each corelet may include a plurality of synapse arrays and a neuron array. Each synapse array may include a plurality of synapses and a synapse array router coupled to synapse outputs in a synapse array. Each synapse may include a synapse input, synapse output; and a synapse memory. A neuron array may include a plurality of neurons, each neuron may include a neuron input and a neuron output. Each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.