公开(公告)号：US20210374249A1

公开(公告)日：2021-12-02

申请号：US16887602

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Bilgiday Yuce ,  Sayak Ray ,  Majid Sabbagh ,  Xueyang Wang ,  Monodeep Kar ,  Hareesh Khattri ,  Jason Fung

IPC: G06F21/57 ,  G06F21/75

Abstract: The present disclosure detects and/or prevents power analysis side-channel attacks without requiring the use of external measurement devices. A first portion of field programmable gate array (FPGA) circuitry is configured to provide emulated hardware device circuitry and a second portion of the FPGA circuitry is configured to provide power monitoring circuitry. The emulated hardware device circuitry and the power monitoring circuitry are coupled to FPGA power distribution network circuitry. The power monitoring circuitry includes time-to-digital converter (TDC) circuitry that includes observation delay buffers to sample a clock propagation delay. Since the voltage supplied to the buffer circuitry affects the propagation delay, the TDC circuitry outputs a binary sequence representative of one or more power delivery parameters to the emulated hardware device circuitry. Analysis circuitry uses the collected data representative of one or more power delivery parameters to determine the susceptibility of the emulated hardware device circuitry to a power analysis side-channel attack.

公开(公告)号：US11860703B1

公开(公告)日：2024-01-02

申请号：US17881110

申请日：2022-08-04

Applicant: Intel Corporation

Inventor： Abhishek Chakraborty ,  Chen Liu ,  Jason Fung ,  Neer Roggel

IPC: G06F21/72 ,  G06F1/30

CPC classification number: G06F1/305 ,  G06F21/72

Abstract: The technology disclosed herein determining one or more vulnerable instructions in workload code and determining one or more additional instructions to be inserted in the workload code based at least in part on a power model of a system bus of a processor, when a power model of a processor is dependent on an order of instructions of workload code, inserting the one or more additional instructions with dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions; and when the power model is not dependent on the order of instructions of workload code, inserting the one or more additional instructions without dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions.