公开(公告)号：US11048626B1

公开(公告)日：2021-06-29

申请号：US16797796

申请日：2020-02-21

Applicant: Intel Corporation

Inventor： Kerry Vander Kamp ,  Jason Voelz ,  James Goffena ,  Robert Branch ,  Mahesh Natu ,  Anand Enamandram

IPC: G06F12/02 ,  G06F12/0802 ,  G06F9/50 ,  G06F12/14

Abstract: Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.