公开(公告)号：US11989074B2

公开(公告)日：2024-05-21

申请号：US17354821

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Anand Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  H03M1/12

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  H03M1/12

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

公开(公告)号：US20210318742A1

公开(公告)日：2021-10-14

申请号：US17354821

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Anand Enamandram ,  Daniel Cartagena ,  Krishnakanth Sistla ,  Jorge P. Rodriguez ,  Efraim Rotem ,  Nir Rosenzweig

IPC: G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3234

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

公开(公告)号：US11048626B1

公开(公告)日：2021-06-29

申请号：US16797796

申请日：2020-02-21

Applicant: Intel Corporation

Inventor： Kerry Vander Kamp ,  Jason Voelz ,  James Goffena ,  Robert Branch ,  Mahesh Natu ,  Anand Enamandram

IPC: G06F12/02 ,  G06F12/0802 ,  G06F9/50 ,  G06F12/14

Abstract: Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.