公开(公告)号：US20240185905A1

公开(公告)日：2024-06-06

申请号：US18547910

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Shuo LIU ,  Yao Zu DONG ,  Qing HUANG ,  Kevin Yufu LI ,  Yipeng YAO ,  Jie YU

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40611 ,  G11C11/408 ,  G11C11/4096

Abstract: A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.