公开(公告)号：US20240213987A1

公开(公告)日：2024-06-27

申请号：US18089026

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Jimin Zhang

IPC: H03K19/17736 ,  H03K19/17704 ,  H03K19/20

CPC classification number: H03K19/1774 ,  H03K19/17716 ,  H03K19/20

Abstract: Adaptive clock gating may provide improved power management of electronic devices. Clock gating may include removing a clock signal to state elements when those state elements are not being used, and the adaptive clock gating may provide improved clock gating for higher-level clock gates operating at increased frequencies. In an example, the adaptive clock gating may enable clock gating for higher-level clock gates within IP blocks that may be otherwise prevented from using clock gating due to timing requirements. The adaptive clock gating may be used to reduce power consumed by the clock distribution of IP blocks, thereby providing improved power efficiency. An adaptive clock gating circuit may include an IP clock frequency control unit with an adaptive clock gating logic circuit. The adaptive clock gating logic circuit may be used to selectively enable or disable high-level clock gates for the target IP based on a selected clock frequency.