公开(公告)号：US20220269303A1

公开(公告)日：2022-08-25

申请号：US17182148

申请日：2021-02-22

申请人： pSemi Corporation

发明人： Gerald ALCORN

IPC分类号： G06F1/08 ,  G05B19/045 ,  H03K19/17704

摘要： Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

公开(公告)号：US11264991B2

公开(公告)日：2022-03-01

申请号：US17104648

申请日：2020-11-25

申请人： The Trustees of Indiana University ,  The United States of America, as represented by the Secretary of the Navy

发明人： Andrew Lukefahr ,  Adam Duncan

IPC分类号： H03K19/173 ,  H03K19/1776 ,  H03K19/17704 ,  H03K19/17728

摘要： A field-programmable gate array (FPGA) architecture capable of performing immutable hardware Root-of-Trust updates and patches. In embodiments, the architecture utilizes the dielectric breakdown mechanism of magneto tunnel junctions (MTJ) to operate both as: 1) multi-time programmable (MTP) configuration memory for reconfigurable FPGA designs, and 2) one-time programmable (OTP) memory for FPGA Root-of-Trust sections.

公开(公告)号：US20210313990A1

公开(公告)日：2021-10-07

申请号：US17349136

申请日：2021-06-16

申请人： Micron Technology, Inc.

发明人： Tony M. Brewer

IPC分类号： H03K19/17756 ,  H01L27/06 ,  H01L27/24 ,  H01L27/11526 ,  H03K19/17764 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  G11C16/04

摘要： A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.

公开(公告)号：US11018671B2

公开(公告)日：2021-05-25

申请号：US16083965

申请日：2017-04-06

申请人： NEC Corporation

发明人： Xu Bai ,  Toshitsugu Sakamoto ,  Yukihide Tsuji ,  Makoto Miyamura ,  Ayuka Tada ,  Ryusuke Nebashi

IPC分类号： H03K19/177 ,  H03K19/17736 ,  H03K19/173 ,  H03K19/17704 ,  H03K19/17784 ,  H03K19/17796

摘要： A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

公开(公告)号：US20200335399A1

公开(公告)日：2020-10-22

申请号：US16916103

申请日：2020-06-29

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC分类号： H01L21/822 ,  H01L27/105 ,  H01L21/683 ,  H01L23/525 ,  H01L21/84 ,  H03K19/17704 ,  H01L25/065 ,  H01L27/11 ,  H01L27/06 ,  H01L27/112 ,  G11C29/00 ,  H01L27/108 ,  H01L21/762 ,  H01L27/02 ,  H03K19/17764 ,  H01L23/544 ,  G11C16/04 ,  H01L29/78 ,  G11C17/14 ,  H03K17/687 ,  H01L25/18 ,  H03K19/17796 ,  H01L27/118 ,  G11C17/06 ,  H03K19/0948 ,  H01L29/786 ,  H01L27/092 ,  H01L23/36 ,  H03K19/17756 ,  H01L21/8238 ,  H01L27/11526 ,  G11C16/12 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/24 ,  H01L27/12 ,  G11C13/00

摘要： A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.

公开(公告)号：US20200266822A1

公开(公告)日：2020-08-20

申请号：US16648820

申请日：2018-09-14

申请人： NEC Corporation

发明人： Yukihide TSUJI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Xu BAI

IPC分类号： H03K19/185 ,  H03K19/173 ,  H03K19/17704 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H03K19/17728 ,  H03K19/17756 ,  G06F7/57

摘要： This logic integrated circuit has a plurality of first switch cells including variable resistance elements and a plurality of second switch cells including variable resistance elements. The logic integrated circuit comprises: a first output port and a second output port; the plurality of first switch cells for switching the electrical connections between a first wire and a third wire; the plurality of second switch cells for switching the electrical connections between a second wire and the third wire; a first control transistor which is connected to the first wire and which is for switching the electrical connections between the first wire and a first power line supplying power to the first wire; and a second control transistor which is connected to the second wire and which is for switching the electrical connections between the second wire and the first power line supplying power to the second wire.

公开(公告)号：US10673439B1

公开(公告)日：2020-06-02

申请号：US16367108

申请日：2019-03-27

申请人： Xilinx, Inc.

发明人： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC分类号： H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

摘要： A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.

公开(公告)号：US10666265B2

公开(公告)日：2020-05-26

申请号：US16146849

申请日：2018-09-28

申请人： Intel Corporation

发明人： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC分类号： H03K19/173 ,  G06F7/38 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17704 ,  H03K19/17758

摘要： An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US10587270B2

公开(公告)日：2020-03-10

申请号：US16439577

申请日：2019-06-12

申请人： Intel Corporation

发明人： Gary Wallichs ,  Sean Atsatt

IPC分类号： H03K19/177 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17704

摘要： Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

公开(公告)号：US11621713B2

公开(公告)日：2023-04-04

申请号：US17408129

申请日：2021-08-20

申请人： Intel Corporation

发明人： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC分类号： H03K19/177 ,  H01L25/065 ,  H03K19/17704 ,  H03K19/17724 ,  H03K19/1776 ,  H03K19/17736 ,  G06F30/30 ,  G06F30/32 ,  G06F30/34

摘要： Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.