公开(公告)号：US20250089228A1

公开(公告)日：2025-03-13

申请号：US18464392

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Meenakshisundaram Ramanathan ,  Krishna Ganesan ,  John Crocker ,  Akitomo Matsubayashi ,  Jianhua Yin ,  Reken Patel

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: Integrated circuit (IC) structures that include static random-access memory (SRAM) and that are fabricated using gate contact patterning after source/drain (S/D) metallization are disclosed. An example IC structure includes a transistor comprising an S/D region and a gate electrode material, an S/D contact in electrical contact with the S/D region, and a gate contact in electrical contact with the gate electrode material. The S/D contact includes a first electrically conductive material, the gate contact includes a second electrically conductive material, and a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, wherein an average grain size or orientation in the portion of the first electrically conductive material is different from an average grain size or orientation in the portion of the second electrically conductive material.