公开(公告)号：US20200210193A1

公开(公告)日：2020-07-02

申请号：US16233035

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Sangeeta BHATTACHARYA ,  Mark DECHENE ,  John FAISTL ,  Jason M. AGRON ,  Sebastian WINKEL ,  Rangeen BASU ROY CHOWDHURY

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

Abstract: A processor includes a set of execution units in an out-of-order execution pipeline, and a hardware profiler in the out-of-order execution pipeline coupled to the set of execution units and to profile instructions executed by the set of execution units, the hardware profiler to generate a profiling interrupt, the profiling interrupt to initiate an optimization of a basic block of instructions in response to determining that a whitelist bit is set corresponding to the basic block of instructions, the whitelist bit to identify the basic block of instructions for immediate optimization.