公开(公告)号：US20240143502A1

公开(公告)日：2024-05-02

申请号：US17958338

申请日：2022-10-01

Applicant: INTEL CORPORATION

Inventor： Mark DECHENE ,  Thomas MULLINS ,  Ryan CARLSON ,  Paula PETRICA ,  Brendan WEST ,  Jonathan JOHNSON ,  Nikhil PATIL

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/601

Abstract: An apparatus and method for implementing a Level 0 cache within a cache subsystem. For example, one embodiment of a processor comprises: a cache subsystem comprising a Level-0 cache; a scheduler to schedule a load operation indicating data to be loaded; and a load hit predictor to predict whether the data indicated by the load operation is stored in the LO cache and to generate a wakeup signal to the scheduler in response to predicting that the data is stored in the LO cache. Some implementations perform store forwarding in response to load operations using a multi-step approach in which a partial linear address check is performed to determine load operations which are eligible for store forwarding. A full address check is performed for those load operations which are eligible in which the address of the load is compared against the address of a youngest older store operation. Mini-MOB implementations are also described including a stale data watchdog function and wakeup signal to schedule dependent operations.

公开(公告)号：US20200210193A1

公开(公告)日：2020-07-02

申请号：US16233035

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Sangeeta BHATTACHARYA ,  Mark DECHENE ,  John FAISTL ,  Jason M. AGRON ,  Sebastian WINKEL ,  Rangeen BASU ROY CHOWDHURY

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

Abstract: A processor includes a set of execution units in an out-of-order execution pipeline, and a hardware profiler in the out-of-order execution pipeline coupled to the set of execution units and to profile instructions executed by the set of execution units, the hardware profiler to generate a profiling interrupt, the profiling interrupt to initiate an optimization of a basic block of instructions in response to determining that a whitelist bit is set corresponding to the basic block of instructions, the whitelist bit to identify the basic block of instructions for immediate optimization.