公开(公告)号：US20240296108A1

公开(公告)日：2024-09-05

申请号：US18572211

申请日：2021-10-14

Applicant: Intel Corporation

Inventor： Qian OUYANG ,  Junjie MAO ,  Yi QIAN ,  Minggui CAO ,  Jian Jun CHEN ,  Junjun SHAN ,  Xiangyang WU

IPC: G06F11/36

CPC classification number: G06F11/3684

Abstract: It relates to an apparatus, a device, a method, and a computer program for generating test cases for a verification of hardware instructions of a hardware device in a hypervisor. The apparatus comprises circuitry configured to generate a transition table based on a specification of the hardware device. The transition table comprises a plurality of entries. Each entry represents a change of a state of the hardware device in response to an event. The circuitry is configured to determine entries of the transition table that are equivalent. The circuitry is configured to generate a plurality of test cases based on the entries of the transition table. At least one entry of the transition table is omitted in the generation of the test cases due to being equivalent to another entry of the transition table.

公开(公告)号：US20240232056A1

公开(公告)日：2024-07-11

申请号：US18571797

申请日：2021-10-15

Applicant: Intel Corporation

Inventor： Junjun SHAN ,  Yi QIAN ,  Xiangyang WU ,  Qian OUYANG ,  Minggui CAO ,  Junjie MAO ,  Jian Jun CHEN

IPC: G06F11/36

CPC classification number: G06F11/3676 ,  G06F11/3684

Abstract: Examples relate to an apparatus, a device, a method, and a computer program for generating a test specification for testing software code of a function under test. The apparatus for generating the test specification for testing software code of a function under test comprises circuitry configured to extract a plurality of symbols from the software code of the function under test, generate a plurality of test vectors with corresponding sets of expected results for the function under test based on the plurality of symbols, and generate a test specification based on the plurality of test vectors and the corresponding sets of expected results.

公开(公告)号：US20240261675A1

公开(公告)日：2024-08-08

申请号：US18570109

申请日：2021-10-14

Applicant: Intel Corporation

Inventor： Minggui CAO ,  Jian Jun CHEN ,  Qian OUYANG ,  Yi QIAN ,  Junjun SHAN ,  Xiangyang WU

IPC: A63F13/355 ,  A63F13/335 ,  H04L67/568

CPC classification number: A63F13/355 ,  A63F13/335 ,  H04L67/568 ,  A63F2300/538

Abstract: A control apparatus (10), control device, control method and computer program for controlling one or more parameters of a hypervisor (100) and an apparatus, device, method, and computer program for a virtual machine (200). The control apparatus (10) comprises circuitry configured to obtain information on respective performance targets of two or more virtual machines (200) being hosted by the hypervisor (100). The circuitry is configured to set the one or more parameters of the hypervisor (100) to one or more initial values. The circuitry is configured to obtain respective results of a benchmark being run in the two or more virtual machines (200), the results of the benchmark indicating a performance of the respective virtual machines (200) with respect to the respective performance targets, with the results of the benchmark being affected by the one or more parameters. The circuitry is configured to adjust the one or more parameters based on the results of the benchmark and based on the respective performance targets. The circuitry is configured to repeat obtaining the respective results of the benchmark and adjusting the one or more parameters until a termination condition is met.

公开(公告)号：US20240202106A1

公开(公告)日：2024-06-20

申请号：US18572214

申请日：2021-10-15

Applicant: Intel Corporation

Inventor： Junjun SHAN ,  Minggui CAO ,  Jian Jun CHEN ,  Qian OUYANG ,  Yi QIAN ,  Xiangyang WU

IPC: G06F11/36

CPC classification number: G06F11/3684

Abstract: Examples relate to an apparatus, a device, a method and a computer program for generating code for test cases for testing a function under test. The apparatus comprises circuitry configured to obtain a diagram representation of the function under test, select a plurality of symbols of interest from the diagram representation of the function under test, the symbols of interest being based on a pre-defined set of symbols of interest, and generate, for the symbols of interest, code of a plurality of test cases based on a pre-defined set of checks related to the pre-defined symbols of interest.