公开(公告)号：US20220200623A1

公开(公告)日：2022-06-23

申请号：US17133609

申请日：2020-12-23

申请人： Intel Corporation

发明人： JAMES GUILFORD ,  VINODH GOPAL ,  DANIEL CUTTER ,  KIRK YAP

IPC分类号： H03M7/40 ,  H03M7/30 ,  G11C15/00 ,  G06F3/06

摘要： Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure.

公开(公告)号：US20200004535A1

公开(公告)日：2020-01-02

申请号：US16024815

申请日：2018-06-30

申请人： Intel Corporation

发明人： KIRK YAP ,  JAMES GUILFORD ,  DANIEL CUTTER ,  VINODH GOPAL ,  DANIIL SOKOLOV

IPC分类号： G06F9/30

摘要： An apparatus and method for loading and storing multiple sets of packed data elements. For example, one embodiment of a processor comprises: a decoder to decode a multiple load instruction to generate a decoded multiple load instruction comprising a plurality of operations, the multiple load instruction including an opcode, source operands, and at least one destination operand; a first source register to store N packed index values; a second source register to store a base address value; execution circuitry to execute the operations of the decoded multiple load instruction, the execution circuitry comprising: parallel address generation circuitry to combine the base address from the second source register with each of the N packed index values to generate N system memory addresses; data load circuitry to cause N sets of data elements to be retrieved from the N system memory addresses, the data load circuitry to store the N sets of data elements in N vector destination registers identified by the at least one destination operand.