公开(公告)号：US09552267B2

公开(公告)日：2017-01-24

申请号：US14564869

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Chee Keong Sim ,  Kai Chong Ng ,  Tze Ming Hau

IPC: G06F9/00 ,  G06F11/22 ,  G06F9/44

CPC classification number: G06F11/2284 ,  G06F9/4401 ,  G06F9/4413

Abstract: Apparatuses, methods and storage medium associated with automatic SATA receiver equalization margin determination and setting, are disclosed. In embodiments, an apparatus may comprise a BIOS configured to determine, during POST, whether a device is attached to one of the SATA ports, and on determination that a device is attached to one of the SATA ports, further determine whether a receiver equalization margin has been set for the device. Additionally, the BIOS may be configured to perform a DTLE training to dynamically determine and set the receiver equalization margin for the device, on determination that a receiver equalization margin has not been set for the device. Other embodiments may be described and/or claimed.

Abstract translation: 公开了与自动SATA接收机均衡裕度确定和设置相关联的装置，方法和存储介质。 在实施例中，设备可以包括被配置为在POST期间确定设备是否连接到其中一个SATA端口并且在确定设备附接到其中一个SATA端口的情况下进一步确定接收机均衡裕度 已设置为设备。 此外，BIOS可以被配置为执行DTLE训练以在确定尚未为该设备设置接收机均衡裕度的情况下动态地确定并设置设备的接收机均衡裕度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11239126B2

公开(公告)日：2022-02-01

申请号：US16487194

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Florence Su Sin Phun ,  Wei Jern Tan ,  Boon Ping Koh ,  Nik Mohamed Azeim Nik Zurin ,  Kai Chong Ng

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.

公开(公告)号：US20210074598A1

公开(公告)日：2021-03-11

申请号：US16487194

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Florence Su Sin Phun ,  Wei Jern Tan ,  Boon Ping Koh ,  Nik Mohamed Azeim Nik Zurin ,  Kai Chong Ng

IPC: H01L23/13 ,  H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.

公开(公告)号：US10779402B1

公开(公告)日：2020-09-15

申请号：US16402992

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Kai Chong Ng ,  Natasya Athirah Abdul Khalid ,  Florence Su Sin Phun ,  Yee Hung See Tau ,  Asmah Truky ,  Ying Ern Ho

IPC: H05K1/02 ,  H01L23/498 ,  G06F1/10

Abstract: A printed circuit board (PCB) includes a dielectric plane and a ground plane parallel to and spaced apart from the dielectric plane. The dielectric plane includes a pair of signal traces and a 3-dimensional (3D) grounded (GND) fence located between the pair of signal traces. The 3D GND fence is electrically connected to the ground plane, and protrudes perpendicularly from the dielectric plane. The 3D GND fence is located equidistant from each of the pair of signal traces, and the 3D GND fence is configured to block electromagnetic interference (EMI) from a first of the pair of signal traces to a second of the pair of the signal traces. The pair of signal traces is configured to form part of a noise-sensitive electronic circuit. The 3D GND fence may have a rectangular configuration.