公开(公告)号：US20250112167A1

公开(公告)日：2025-04-03

申请号：US18375327

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Kimberly Pierce ,  Marni Nabors ,  Nidhi Khandelwal ,  Keith Zawadzki

IPC: H01L23/544 ,  G03F7/09 ,  H01L21/768 ,  H01L23/528 ,  H01L23/58

Abstract: An integrated circuit (IC) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. A functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. The IC device may include multiple such functional blocks spanning lithographic fields. The lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as registration marks and metrology structures. The multiple lithographic fields may be or include high numerical aperture extreme ultraviolet lithographic fields. The lithographic seam may interface with wafer finishing collaterals (such as guard rings).