公开(公告)号：US20210200540A1

公开(公告)日：2021-07-01

申请号：US16729369

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Kermin E. CHOFLEMING ,  Chuanjun ZHANG ,  Daniel TOWNER ,  Simon C. STEELY, JR. ,  Benjamin KEEN

IPC: G06F9/30

Abstract: Systems, methods, and apparatuses relating to fused operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes a plurality of processing elements; a network between the plurality of processing elements to transfer values between the plurality of processing elements; and a processing element of the plurality of processing elements comprising: a first plurality of input queues having a multiple bit width coupled to the network, at least one first output queue having the multiple bit width coupled to the network, operation circuitry coupled to the first plurality of input queues having the multiple bit width, a sign modification circuit coupled to the first plurality of input queues having the multiple bit width, and a configuration register within the processing element to store a configuration value comprising a sign modification field that causes the sign modification circuit to modify a sign bit of a value from the first plurality of input queues according to the sign modification field to create a sign modified value, and the configuration value causes the operation circuitry to perform a selected operation of a plurality of operations on a value from the first plurality of input queues and the sign modified value to create a resultant value, and store the resultant value in the at least one first output queue.