公开(公告)号：US20200004538A1

公开(公告)日：2020-01-02

申请号：US16024849

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Kermin E. FLEMING, JR. ,  Ping ZOU ,  Mitchell DIAMOND ,  Benjamin KEEN

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/82 ,  G06F9/50

Abstract: Systems, methods, and apparatuses relating to conditional operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes an output buffer of a first processing element coupled to an input buffer of a second processing element via a first data path that is to send a first dataflow token from the output buffer of the first processing element to the input buffer of the second processing element when the first dataflow token is received in the output buffer of the first processing element; an output buffer of a third processing element coupled to the input buffer of the second processing element via a second data path that is to send a second dataflow token from the output buffer of the third processing element to the input buffer of the second processing element when the second dataflow token is received in the output buffer of the third processing element; a first backpressure path from the input buffer of the second processing element to the first processing element to indicate to the first processing element when storage is not available in the input buffer of the second processing element; a second backpres sure path from the input buffer of the second processing element to the third processing element to indicate to the third processing element when storage is not available in the input buffer of the second processing element; and a scheduler of the second processing element to cause storage of the first dataflow token from the first data path into the input buffer of the second processing element when both the first backpres sure path indicates storage is available in the input buffer of the second processing element and a conditional token received in a conditional queue of the second processing element from another processing element is a first value.

公开(公告)号：US20220107911A1

公开(公告)日：2022-04-07

申请号：US17550875

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Kermin E. FLEMING ,  Simon C. STEELY ,  Kent D. GLOSSOP ,  Mitchell DIAMOND ,  Benjamin KEEN ,  Dennis BRADFORD ,  Fabrizio Petrini ,  Barry TANNENBAUM ,  Yongzhi ZHANG

IPC: G06F13/40 ,  G06F9/30 ,  G06F15/78

Abstract: Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

公开(公告)号：US20210200540A1

公开(公告)日：2021-07-01

申请号：US16729369

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Kermin E. CHOFLEMING ,  Chuanjun ZHANG ,  Daniel TOWNER ,  Simon C. STEELY, JR. ,  Benjamin KEEN

IPC: G06F9/30

Abstract: Systems, methods, and apparatuses relating to fused operations in a configurable spatial accelerator are described. In one embodiment, a hardware accelerator includes a plurality of processing elements; a network between the plurality of processing elements to transfer values between the plurality of processing elements; and a processing element of the plurality of processing elements comprising: a first plurality of input queues having a multiple bit width coupled to the network, at least one first output queue having the multiple bit width coupled to the network, operation circuitry coupled to the first plurality of input queues having the multiple bit width, a sign modification circuit coupled to the first plurality of input queues having the multiple bit width, and a configuration register within the processing element to store a configuration value comprising a sign modification field that causes the sign modification circuit to modify a sign bit of a value from the first plurality of input queues according to the sign modification field to create a sign modified value, and the configuration value causes the operation circuitry to perform a selected operation of a plurality of operations on a value from the first plurality of input queues and the sign modified value to create a resultant value, and store the resultant value in the at least one first output queue.