公开(公告)号：US20230353508A1

公开(公告)日：2023-11-02

申请号：US18220206

申请日：2023-07-10

Applicant: Intel Corporation

Inventor： Kapil SOOD ,  Patrick CONNOR ,  Scott P. DUBAL ,  James R. HEARN ,  Brendan RYAN ,  Chris MACNAMARA ,  Conor WALSH ,  David HUNT ,  John J. BROWNE ,  Kevin LAATZ

IPC: H04L49/00 ,  H04L47/625

CPC classification number: H04L49/3018 ,  H04L47/626

Abstract: Examples described herein relate to a system within a package. In some examples, the system includes a communication fabric and circuitry to adjust a packet throughput rate associated with the communication fabric based at least in part on incoming receive rate across multiple input ports and fabric usage. In some examples, the communication fabric is to communicatively couple devices in the package including one or more of: an accelerator, a processor, a memory, or a network interface device.

公开(公告)号：US20230035142A1

公开(公告)日：2023-02-02

申请号：US17966441

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  David HUNT ,  Kevin LAATZ ,  Anatoly BURAKOV ,  Bruce RICHARDSON ,  Conor WALSH ,  John J. BROWNE

IPC: G06F9/50

Abstract: A method is described. The method includes polling a queue a plurality of times over a plurality of intervals, where, the queue feeds work items to a processor. The method includes determining, from the polling, respective work item flow metrics for the plurality of intervals. The method includes determining a processor's performance setting based on the plurality of respective work item flow metrics.

公开(公告)号：US20250013493A1

公开(公告)日：2025-01-09

申请号：US18889249

申请日：2024-09-18

Applicant: Intel Corporation

Inventor： Chris MACNAMARA ,  John J. BROWNE ,  Nilanjan PALIT ,  Chetan HIREMATH ,  Rory SEXTON ,  Conor WALSH ,  Kevin LAATZ ,  Andriy GLUSTSOV ,  Peter McCARTHY ,  Katelyn DONNELLAN ,  Vishal DEEP AJMERA ,  David HUNT ,  Gordon NOONAN

IPC: G06F9/48

Abstract: Examples described herein relate to circuitry to: monitor utilization data for a plurality of processes; determine one or more priority levels associated with at least one of the plurality of processes based on policy parameters; and adjust a frequency of operation of the interface circuitry based on the monitored utilization data and the determined priority levels of the processes. In some examples, adjust the frequency of operation of the interface circuitry is to prioritize frequency of operation requested by a higher priority workload over a frequency of operations requested by a lower priority workload.

公开(公告)号：US20190280991A1

公开(公告)日：2019-09-12

申请号：US16414502

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Jasvinder SINGH ,  Pablo DE LARA GUARCH ,  Kevin LAATZ ,  CIARA POWER ,  Greg CURRAN ,  John J. BROWNE

IPC: H04L12/861 ,  H04L12/713 ,  H04L12/851

Abstract: At a network interface, received packets are classified according to priority level or traffic class. Based on an assigned priority level, a received packet can be allocated to use a descriptor queue associated with the assigned priority level. The descriptor queue can have an associated buffer region in which portions of received packets are stored. The length of the descriptor queue can be dependent on the priority level such that a highest priority descriptor queue can be longer than a lowest priority descriptor queue. The size of the buffer can be dependent on the priority level such that a highest priority level can be assigned a separate buffer space of different size than that assigned to a lower priority level. A polling rate for a descriptor queue can be configured based on a priority level such that a highest priority level descriptor queue can be polled more frequently than a polling of a lower priority level descriptor queue.